In the field of electronic devices such as computer systems, digital handy terminals, and so on, non-volatile memory devices have been considered to be an important component in recent years. In this electronic device, there is increasingly a demand for memory devices to have a large storage capacity. In order to satisfy this demand it is very important to improve device integration. However, due to many limits, present process technologies have not allowed for a dramatic improvement of integration. To overcome this problem, methods for doubling storage capacity without needing to improve integration have been developed. As is well-known, these methods include a technique for storing multi-bit (multi-level) data in one memory cell.
Typical examples of memories for storing multi-bit data are disclosed in U.S. Pat. No. 6,122,188 entitled “NON-VOLATILE MEMORY DEVICE HAVING MULTI-BIT CELL STRUCTURE AND A METHOD OF PROGRAMMING SAME” and U.S. Pat. No. 5,673,223 entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH MULTIPLE WORD LINE VOLTAGE GENERATOR”.
Sense amplification circuits have been widely used to read/write multi-bit data stored in memory cells. The sense amplification circuits sense and amplify data stored in a selected memory cell by comparing an amount of a current flowing through a selected memory cell with a reference current. To generate the reference current, generally, a reference memory cell is arranged in the sense amplification circuit. For example, when one memory cell stores a single-bit data, one reference memory cell is therein. In addition, when one memory cell stores 2-bit data, three reference memory cells are therein. The reference memory cells located in the sense amplification circuit should be implemented to have different threshold voltages.
If sense amplification circuits are needed in multi-bit memory devices, multiplicity of the reference memory cells may be arranged in each of the sense amplification circuits. In the multi-bit memory devices, each of the memory cells has any one of a multitude of threshold voltage distributions, which correspond to multi-bit states, respectively. Additionally, each of the memory cells has a small margin in comparison with a single-bit memory device. Therefore, in order to read multi-bit data employing a small margin, there is a need to more precisely control threshold voltages of the reference memory cell. Accordingly, it is important to perform a test operation for deciding whether each of the reference memory cell has a required threshold voltage so as to strictly control threshold voltages of the reference memory cells in the sense amplification circuits. Furthermore, as is well-known, the reference memory cell in the sense amplification circuit needs several lay-out regions (e.g., a special region for the reference memory cell or a special well region for high-voltage transistors used to control the reference memory cell).
Embodiments of the invention address these and other limitations in the prior art.